Clock and data recovery (CDR) is widely used in high speed Serializer-Deserializer (SerDes) systems to recover the embedded clock information from a received data signal. In a typical CDR implementation, a phase detector (PD) and a phase interpolator PI are provided, where a first order path (i.e. a phase path) gain and a second order path (i.e. frequency path) gain are implemented.
In the CDR locked state, the phase path tracks the instantaneous phase difference between the received data and the local clock within its loop bandwidth and loop gain range, while the frequency path periodically updates the PI to track the averaged frequency offset within its tracking range.
The CDR phase detector only provides phase difference information, but not frequency difference information, measured by parts per million (ppm). When the frequency difference between the transmitted signal and the local clock is outside the CDR frequency capture range, the CDR frequency path could lock to an incorrect frequency, i.e. an incorrect ppm offset, especially when the incoming signal also contains a large sinusoidal clock jitter. When this happens, the recovered data may be wrong.
Accordingly, there is a need for a clock and data recovery circuit that reduces locking to an incorrect frequency.